In clocked systems, the clock period is fairly reliable. However, the division of the clock period between intervals of high signal duration and of low signal duration—i.e., the duty cycle—whether in a clock signal or a data signal, may be less reliable. For example, the JEDEC DDR4 memory standard allows for duty-cycle deviation of ±2% of the clock period. Anecdotal reports suggest, however, that in some systems duty-cycle distortion may be as much as ±10%. That would mean, for example, that in a clock signal that is supposed to be high during 50% of the clock period and low during the other 50% of the clock period, the actual signal may be high during 55% of the clock period and low during the other 45% of the clock period, or vice-versa.
This is of particular concern in double data-rate memory (or higher data-rate memories) in which data are read on both rising and falling edges of a clock or strobe signal, because duty-cycle distortion in the clock signal can lead to duty-cycle distortion in the data signal. And if data are read on both rising and falling edges of a clock or strobe signal, and the data signal is not alternating between low and high on time, one or both of the rising and falling clock edges may intersect the wrong data value.
Adjusting the duty cycle is relatively straightforward once the need for adjustment is recognized. However, determining the duty cycle, thereby to recognize when adjustment is needed, is less straightforward.